1. Field of the Invention
The embodiments of the invention generally relate to optimizing power usage in integrated circuit designs and more particularly to a method that moves the cut point after manufacture.
2. Description of Related Art
U.S. Patent Publication 2008/0034337 (the complete disclosure of which is incorporated herein by reference) discloses that manufacturing variations may cause one or more parameters to vary between integrated circuits that are formed according to the same design. These variations can affect chip operating frequency (i.e., switching speed). For example, due to variations in the equipment, operators, position on a wafer, etc., a specific parameter may vary between chips built on the same wafer, chips built on different wafers in the same lot and/or on chips built on different wafers in different lots. If this parameter is, for example, line width, then the channel width of the transistors on each chip may be different such that the performance varies (e.g., faster or slower). Chips that are fabricated either at the “slow” end or the “fast” end of a process distribution (e.g., a process-temperature-variation (PVT) space) may not be desirable. For example, chips that are fabricated at the “slow” end of such a process distribution may not meet the desired performance specification (i.e., may not have a fast enough switching speed), whereas chips fabricated at the “fast” end of this process distribution may exhibit excessive power and leakage current. Thus, conventional teachings describe a process to run faster parts at lower voltage and slower parts at higher voltage, in order to reduce the maximum power for the distribution of parts. The division between the fast and slow portions of the distribution (i.e. the cutpoint), is generally determined apriori during the design phase.